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Ordering number:ENN *3932
CMOS IC
LC7073, 7073M
Error Detection and Correction ICs for RDS Demodulators
Preliminary Overview
The LC7073 and LC7073M are error detection and correction ICs that provide an easy interface to the LA2230 and LA2231 radio data system (RDS) demodulators. Both devices incorporate an on-chip oscillator that connects directly to an external ceramic resonator. The LC7073 and LC7073M provide group synchronization, selectable error detection and correction, output clock polarity selection, a block data start signal output and an error output that signals error correction failures. The LC7073 and LC7073M operate from a 5 V supply and are available in 18-pin DIPs and MFPs, respectively.
Package Dimensions
unit:mm 3007B-DIP18
[LC7073]
24.0 18 10
7.62 6.4
1
9
* RDS error detection and correction. * Easy interface with LA2230 and LA2231 demodulator ICs. * Serial data transfer system. * Group synchronization capability. * Selectable error detection and correction. * Output clock polarity selection. * Block data start output. * Error output. * On-chip oscillator. * 5 V supply. * 18-pin DIP (LC7073) and 18-pin MFP (LC7073M). Pin Assignment
(1.84)
2.54
0.5
1.2
0.51min
SANYO : DIP18
unit:mm 3095-MFP18
[LC7073M]
18 10
12.6
0.35
1.27
1.22
0.1 1.5
SANYO : MFP18
Top view
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
71901TN (KT)/5281JN(US) No.3932-1/9
0.625
1
9
1.8max
0.15
6.35 7.6
5.4
3.3
Features
3.85max
(3.25)
0.25
LC7073, 7073M
Block Diagram
Pin Function
Number Name Equivalent circuit Description
1
OSC1
External ceramic resonator connection 1
2 3
VSS1 VSS2
Ground Ground
4
RES
Schmitt-trigger reset input. Held LOW for a minimum of 4 clock cycles
5
CKIN
Serial data input clock. Connects to RDS demodulator output clock
6
DIN
Serial data input. Connects to RDS demodulator data output
7
COREN
Error-correction enable input. LOW disables error correction and HIGH enables error correction
Continued on next page.
No.3932-2/9
LC7073, 7073M
Continued from preceding page.
Number Name Equivalent circuit Description
8
CKPOL
Serial data output clock polarity select input
9
VDD
5 V supply
10
REC
Serial data receive detect output. LOW while receiving, after sync detection. High impedance when not receiving. High impedance after reset
11
DSTCTL
Data start control input. LOW initiates data start for second block, and HIGH, for all blocks
12
COR
Error-correction enabled/disabled output. LOW when error correction occurs and HIGH when no error correction occurs. High impedance after reset
13
ERR
Error-detect output. LOW when error correction fails. High impedance when error correction does not fail. High impedance after reset
14
DST
Serial data start output. LOW indicates no data start, and HIGH, data start. HIGH after reset
15
DOUT
Serial data output. HIGH after reset
16
CKOUT
Serial data output clock
17
VSS3
Ground
18
OSC2
External ceramic resonator connection 2
No.3932-3/9
LC7073, 7073M Specifications
Absolute Maximum Ratings at Ta = +25C, VSS1, VSS2, VSS3 = 0V
Parameter Maximum supply voltage OSC2, DST, DOUT and CKOUT output voltage REC, COR and ERR output voltage RES and OSC1 input voltage CKIN, DIN, COREN, CKPOL and DSCTL input voltage REC, COR and ERR output current DST, DOUT and CKOUT output current Output pins total current DIP allowable power dissipation MFP allowable power dissipation Operating temperature Storage temperature Symbol VDD max VO1 VO2 VI1 VI2 IO1 IO2 IO Pd max Pd max Topr Tstg DIP: Ta=-40 to +85C MFP: Ta=-40 to +85C Conditions Ratings - 0.3 to +7.0 - 0.3 to VDD+0.3
- 0.3 to +15 - 0.3 to VDD+0.3 - 0.3 to +15 20 - 2 to +20 - 14 to +90 to 280
Unit V V V V V mA mA mA mW mW C C
to 200
- 40 to +85 - 55 to +125
Reommended Operating Conditions at Ta = -40 to +85C, VSS1, VSS2, VSS3 = 0V, VDD = 4.5 to 6.0V
Parameter Supply voltage range CKIN, DIN, COREN, CKPOL and DSCTL highlevel input voltage RES and OSC1 high-level input voltage CKIN, DIN, COREN, CKPOL and DSCTL lowlevel input voltage RES low-level input voltage Symbol VDD VIH1 VIH2 VIL1 VIL2 Conditions Ratings min 4.5 0.7VDD 0.8VDD VSS VSS typ max 6.0 13.5 VDD 0.3VDD
0.25VDD
Unit V V V V V
Electrical Characteristics at Ta = -40 to +85C, VSS1, VSS2, VSS3 = 0V, VDD = 4.5 to 6.0V
Parameter CKIN, DIN, COREN, CKPOL and DSCTL highlevel input current CKIN, DIN, COREN, CKPOL and DSCTL lowlevel input current RES low-level input current DST, DOUT and CKOUT high-level output voltage REC, COR, ERR, DST, DOUT and CKOUT low-level output voltage REC, COR and ERR output leakage current RES hysteresis voltage Supply current Oscillator stabilization time Symbol IIH1 IIL1 IIL2 VOH VOL IOFF VHYS IDD tCFS See note 2. See figure 7. VI=13.5V VI=VSS VI=VSS IOH=- 50A IOH=- 10A IOL=10mA IOL=1.8mA, See note 1. VO=13.5V VO=VSS - 1.0 0.1VDD 4 10 10 - 1.0 - 45
VDD- 1.2 VDD- 0.5
Conditions
Ratings min typ max 5.0
Unit A A
- 10
A V 1.5 0.4 5.0 V A V mA ms
Note 1. Idle pins have output currents less than 1mA. 2. Oscillator running, VI=VDD, IO=0mA
No.3932-4/9
LC7073, 7073M
Timing Diagrams The relationship between the LC7073 and LC7073M input data (RDS demodulated data output) and output data is shown in figure 1.
Figure 1. Input and output data Note The dotted lines show data start (DST) pulses when the data start control (DSTCTL) is LOW. The serial output data is delayed by one block between input and output. The error (ERR) and correction (COR) signals remain active if errors are detected continually. Serial Output Data Timing and Format The following list shows the symbols used in the serial output data string in figure 2. S E F OE OF A/B B0, B1 D0 to D15 Start bit (normally 0) Error flag (See table 1.) Correction flag (See table 1.) Offset E (normally 0, not used) Offset F (normally 0, not used) Group. 0-group A, 1-group B Block bits. 00-1st block, 01-2nd block, 10-3rd block, 11-4th block Output data
Table 1. Error and correction flags
Indication No error Error corrected Not correctable E 0 0 1 F 0 1 x
Note x = don't care
No.3932-5/9
LC7073, 7073M
Figure 2. Serial output data format and timing CKPOL Input Read Delay CKPOL is read 1 ms after a reset as shown in figure 3.
Figure 3. CKPOL input read delay
No.3932-6/9
LC7073, 7073M
COREN and DSTCTL Input Read COREN and DSTCTL are monitored at intervals of one input clock cycle, and their logic states can be changed at any time. During sync detection, a change in input state occurs if either pin remains steady for four successive clock intervals as shown in figure 4.
Figure 4. Input read during sync detection After sync detection a change in input state occurs if either COREN or DSTCTL remains steady for four successive input data blocks as shown in figure 5.
Figure 5. Input read after sync detection Design Notes Oscillator specifications are shown in table 2 and figure 6. Oscillator stabilization delay is shown in figure 7. Reset input circuitry is shown in figure 8. Supply rise time versus RES delay is shown in figure 9. Table 2. Oscillator capacitor values
4 MHz resonator type Murata-CSA4.00MG Kyocera-KBR4.0M C1, C2 30 pF 10% 30 pF 10%
OSC1
OSC2
C1
Ceramic resonator
C2
Figure 6. Oscillator circuit
VDD 4.5V 0V OSC
tCFS tCFS is the oscillator stabilization time
Figure 7. Oscillator stabilization delay
No.3932-7/9
LC7073, 7073M
VDD
VDD RES C=0.1F
Figure 8. Reset input
Start point VDD 4.5V RES 1.125V (0.25VDDmin) 0.8VDD
Oscillator stabilization time (10 to 100 ms)
Figure 9. Supply rise time vs. reset delay A minimum delay of 10 ms should be allowed for oscillator stabilization. A 10 to 100 ms reset delay is generated using a 0.1 F reset capacitor, C. A larger capacitor should be used if the supply rise time is longer.
Figure 10. System block diagram Device Comparison The LC7070N, LC7070M and LC7071NM have identical basic functions, pinouts and input/output timing to those of the LC7073 and LC7073M. Their respective packages and output circuitry are compared in table 3. Table 3. Device comparison
Device LC7070N LC7070NM LC7071NM LC7073 LC7073M Package 18-pin DIP 18-pin MFP 18-pin MFP 18-pin DIP 18-pin MFP Totem-pole using MOS transistors Open-drain Output type
The differences in output data format between the LC7070N/LC7070NM/LC7071NM and LC7073/LC7073M are as follows. Offset Words E and F The LC7070N/LC7070NM/LC7071NM recognizes offset words E and F and performs group sync detection. The LC7073/ LC7073M does not recognize offset words E and F-it only detects A, B, C, C' and D. Input Data Bits If all data bits are 0, the LC7070N/LC7070NM/LC7071NM only recognizes offset word E. The LC7073/LC7073M does not recognize the offset word E block. No sync detection occurs if all input data bits are 0. Once data cutoff has been determined, output data stops and the sync cutoff sequence begins.
No.3932-8/9
LC7073, 7073M
Sync Detection Method The LC7070N/LC7070NM/LC7071NM searches for 5 consecutive blocks in the correct sequence within each group of 12 blocks. The LC7073/LC7073M searches for 2 consecutive blocks in the correct sequence within each group of 3 blocks. Data Output After Sync Detection The LC7070N/LC7070NM/LC7071NM starts data output with the first block (offset A) directly after the last block in the sync detection group. If sync detection occurs during the first block (offset A), the LC7073/LC7073M starts data output with the second block (offset B). If sync detection occurs during the second or third block (offset B or C), and finishes before the end of the fourth block (offset D), the LC7073/LC7073M starts data output with the first block (offset A) of the second group. Sync Error A sync error occurs if no offset word is detected for more than five consecutive blocks. This applies to both the LC7070N/ LC7070NM/LC7071NM and LC7073/LC7073M. Error Correction In error-correction mode, an error of less than 5 bits is corrected to an accuracy of 5 bits. This applies to both the LC7070N/LC7070NM/LC7071NM and the LC7073/LC7073M. Precaution Note that the solder-dip method should not be used for the LC7073M (MFP).
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of July, 2001. Specifications and information herein are subject to change without notice.
PS No.3932-9/9

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